What it is
A serious circuit workbench
RedByte is not a toy simulator and not a Vivado replacement. It is a structured browser IDE for supported digital logic work on the Basys3 path.
Proof-backed FPGA workflow
RedByte is a digital logic and FPGA workbench.
Design a circuit, prove behavior with visible Verify evidence, bind signals to Basys3 pins, and export a Vivado-ready package with an honest trust state.
01
Project
Orient, load starters, and see readiness truth.
02
Design
Author and inspect the circuit graph.
03
Verify
Run Compare checks and waveform-backed proof.
04
Map Pins
Bind design I/O to real Basys3 resources.
05
Export
Generate the Vivado handoff package.
What it proves
Evidence before trust
Trusted Export depends on current Verify evidence and current mapping. Draft Export is allowed, but it is intentionally labeled as draft.
Where Vivado fits
Downstream toolchain
RedByte generates VHDL, XDC, Tcl, README, and project handoff files. Vivado still owns synthesis, implementation, bitstream generation, board programming, and hardware logs.
Run locally
Start the IDE from this repo
Use pnpm. Do not run npm install in this workspace.
pnpm install
pnpm dev
# production-style preview
pnpm --filter @redbyte/playground build
pnpm preview
Course lane
Use the IDE workflow
Open the IDE, load a starter or project, run Verify Compare, map Basys3 pins, then use Export for the Vivado handoff package.
Project -> Design -> Verify
Map Pins -> Export -> Vivado
Evidence ladder
E0/E1/E2/E3 stay separate
E0
RedByte generated the export package.
E1
Vivado synthesis, implementation, and bitstream completed.
E2
The bitstream programmed a Basys3 target.
E3
Physical board behavior was observed against expected controls and outputs.
Current readiness
Honest hardware status
Controlled bench work has E1/E2 evidence for selected Basys3 rows. Final E3 closure is still manual-observation gated for open rows, so RedByte must not claim broad board-behavior proof from programming logs alone.
Vivado setup
Full hardware loop requirements
Use AMD Vivado 2024.2 for the Basys3 handoff. A physical Basys3 board is required for E2 programming and E3 observation. Without Vivado or the board, RedByte still runs locally as a design, verify, map, and export workbench.
Export to Vivado
Expected handoff path
Inside RedByte: Verify with Compare checks, map pins, open Export, download the Vivado Kit, then open the generated project in Vivado.
Limitations
Current boundaries
Basys3 is the supported board. Multi-clock, falling-edge, active-low reset, asynchronous sequential logic, and broad board families are outside the current release boundary.