RedByte

Digital logic and FPGA coursework

A focused engineering workbench from circuit to handoff.

RedByte is a digital logic and FPGA workbench. Design a circuit, check its behavior, map Basys3 pins, and prepare a clear Vivado package without hiding the proof boundary.

Open IDE

Five-stage workflow

One job at a time, from setup through submission files.

01Project

Choose a lab, starter, or saved project.

02Design

Build and inspect the circuit.

03Verify

Compare expected and observed behavior.

04Map Pins

Assign design signals to Basys3 resources.

05Export

Prepare the browser-E0 handoff package.

Built for engineering work

RedByte is not a toy simulator and not a Vivado replacement. It is the browser workbench for supported digital logic design, verification, mapping, and package preparation.

E0

RedByte can establish that the package was generated from the current project state.

Vivado owns the hardware loop

E1 synthesis and implementation, E2 programming, and E3 physical observation remain downstream evidence. A physical Basys3 board is required for E2 programming and E3 observation.

Flow

Project -> Design -> Verify -> Map Pins -> Export -> Vivado

Run RedByte locally

Use the pnpm workspace and the repository-pinned Node runtime. RedByte source and maintained course docs are the truth. Generated outputs support evidence but do not expand release claims.

pnpm install pnpm dev